Ram with pre-input register logic

Abstract

A synchronous SRAM (or DRAM or other logic) chip with input registers (or latches) associated with the chip memory cell array input lines, where there is logic associated with the registers, locates the logic gates upstream of the registers and connected to the D input of each register. Hence the logic gates not only provide the needed logic function, but also provide the necessary delay to meet the specified hold time delay in synchronous circuits. This reduces the logic function after the input registers and hence improves the clock-to-output access time of the chip.