Three input arithmetic logic unit employing carry propagate logic

Abstract

A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The current instruction drives an instruction decoder (250, 245) that generates functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals and a carry input produce a bit resultant and a carry output to the next bit circuit. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performing a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use. The three input arithmetic logic unit (230) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit circuit (400). This carry input is determined by the combination being formed, and generally is '1' only during subtraction. The carry input may be specified in the special purpose data register (D0) for certain instructions.