The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 1996

Filed:

Apr. 15, 1993
Applicant:
Inventors:

John J Wooldridge, Manhattan Beach, CA (US);

Irwin L Newberg, Northridge, CA (US);

Joseph P Smalanskas, Westchester, CA (US);

Ronald I Wolfson, Los Angeles, CA (US);

Assignee:

Hughes Aircraft Company, Los Angeles, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01Q / ;
U.S. Cl.
CPC ...
342368 ; 342372 ; 3437 / ;
Abstract

An electronic device operating in the microwave frequency range having components disposed in a plurality of planes, wherein the planes are stacked vertically. The electronic device is a T/R module or element forming a part of a subarray used in an active array radar. The T/R module or element comprises a transmit chip, a receive chip, low noise amplifiers, a phase shifter, an attenuator, switches, dc power supply, interconnects that interconnect the foregoing components and logic circuits to control the foregoing components. The components when stacked in a 3-D package are disposed behind a radiator or antenna, which transmits and receives the microwave signals. Behind the T/R module or element is a manifold which provides input and output to and from the T/R module or element. The microwave chips of the T/R module are monolithic microwave integrated circuit chips and control logic, which are disposed in an aluminum nitride substrate and coated with a conformal hermetic coating. The 3-D chip package can optionally include micro channel cooling by adding additional layers. The integrated circuits also employ a flip chip design for mounting to the wafers. Optional photonic interconnects could be used for communication between levels in the 3-D package and can be used between subarrays as a manifold.


Find Patent Forward Citations

Loading…