The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 1996

Filed:

Jan. 04, 1994
Applicant:
Inventor:

Sajol C Ghoshal, Orangevale, CA (US);

Assignee:

Level One Communications, Inc., Sacramento, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L / ; H03D / ;
U.S. Cl.
CPC ...
327158 ; 327150 ; 327308 ; 331179 ;
Abstract

A circuit for attenuating phase jitter on an incoming clock signal includes a digital frequency synthesizer, and a phase lock loop including a phase detector. The digital phase detector compares the phase relationship between an incoming signal and a clock signal generated by the digitally controlled frequency synthesizer and produces an output signal proportional to the phase difference. The output signal comprises both a direction indicator and a magnitude indicator for controlling the digitally controlled frequency synthesizer. One of a plurality of phases of a voltage controlled oscillator (VCO) are selected in response to the output signal to alter the frequency of the clock signal.


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