The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 1996

Filed:

Oct. 04, 1994
Applicant:
Inventor:

Michael Geagan, Wayne, PA (US);

Assignee:

ADAC Laboratories, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01T / ; G01T / ;
U.S. Cl.
CPC ...
25036302 ; 250369 ;
Abstract

A gamma camera PMT channel amplification integration circuit having multiple separate and independently triggerable integrators. A multiple number (e.g., two) of separate integrators are placed on each PMT channel for independently integrating separate gamma events. By providing multiple separate integrators per channel, problems associated with pulse pile up are reduced since the system can simultaneously integrate with respect to multiple (e.g., two) gamma events. The farther apart spatially the event occurs, the more accurate the resulting integration becomes. The dual integrators are coupled to supply their integration results to a two stage series connected latch circuit. On a first trigger, a first available integrator is reset and at the end of integration, the result is placed into the first stage latch. If a second trigger occurs before the completion of the first integration, then the second integrator, if available, is triggered (e.g., initialized, reset, etc.) and can integrate the PMT channel signal separately from the first integrator. At the end of the second integration the result is placed in the first stage latch. As data is placed in the first stage of the latch, information moves serially to the second stage and eventually to a digital event processor circuit. Trigger pulses are sent uniformly to each channel amplification integration circuit.


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