Optimized translation lookaside buffer slice having stored mask bits

Abstract

An optimized translation lookaside buffer (TLB) utilizes a least-recently-used algorithm for determining the replacement of virtual-to-physical memory translation entries. The TLB is faster and requires less chip area for fabrication. In addition to speed and size, the TLB is also optimized since many characteristics of the TLB may be changed without significantly changing the overall layout of the TLB. A TLB generating program may thus be used as a design aid. The translation lookaside buffer includes a level decoding circuit which allows masking of a variable number of the bits of a virtual address when it is compared to values stored within the TLB. The masking technique may be used for indicating a TLB hit or miss of a virtual address to be translated, and may also be used for invalidating selected entries within the TLB. The TLB also implements a pipelining technique wherein a LRU comparator compares the least significant bits of a LRU counter at the same time when the most significant bits of the LRU counter are being incremented. Finally, an address decoder is provided within the TLB for indexing each slice during a test mode to check for malfunctions.