The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 1996
Filed:
Jan. 19, 1993
Ronald L Williams, San Marcos, CA (US);
Ogden J Marsh, Carlsbad, CA (US);
Steven E Shields, San Diego, CA (US);
Hughes Aircraft Company, Los Angeles, CA (US);
Abstract
A silicon dioxide etch stop layer (30) is formed on an inner surface (28b) of a monocrystalline silicon layer (28), and a silicon carrier wafer (52) is bonded to the etch stop layer. The exposed inner surface (28a) of the monocrystalline layer (28) is uniformly thinned to approximately 4 micrometers. Front electrodes (20) in the form of heavily doped areas, and microelectronic transistor driver devices (42) for the electrodes (20) are integrally formed on the outer surface (28a) of the monocrystalline layer (28). A front plate (12) is bonded to the outer surface (28a) of the monocrystalline layer (28), and the carrier (52) is removed. The central portion of the etch stop layer (30) is removed from the inner surface (28b) of the monocrystalline layer (28), and the exposed central portion (28c) of the layer (28) is uniformly thinned to approximately 400 angstroms using plasma assisted chemical etching. A back plate (14 ) having a back electrode (16) formed thereon is adhered to the unetched peripheral portion (28d) of the inner surface (28b) of the monocrystalline layer (28) to define a sealed space (24) between the front and back electrodes (12,14) which is filled with liquid crystal material (26). Large scale integrated driver circuitry (38,40) is fabricated in the peripheral portion (28d) of the layer (28) laterally external of the back plate (14) and externally interconnected by via holes (28g,28h) and wirebonds (44,45).