The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 1996
Filed:
Nov. 19, 1993
Edwin F Johnson, Sunnyvale, CA (US);
Douglas G Lockie, Monte Sereno, CA (US);
Clifford A Mohwinkel, San Jose, CA (US);
Endgate Technology Corporation, Sunnyvale, CA (US);
Abstract
A Dual-Sided Push-Pull Amplifier for providing a high-gain yet low-cost amplifier capable of operating at frequencies extending above 1 GHz is disclosed. The present invention may be used in any application in which low cost amplification may be desired, including transmitters, antenna arrays, radars, light wave modulators, mixers, local oscillators, driver amplifiers and microwave ovens. One of the preferred embodiments of the invention (10d/10e) utilizes two pairs of field effect transistors (FETs) (22U and 22L & 24U and 24L) mounted in registration on both faces (12a & 12b) of a dual-sided dielectric substrate (12). The sources (22US and 22LS & 24US and 24US) on both faces of the FETs (22 & 24) are electrically coupled and are located at a minimum distance from their mates on the opposite faces of the substrate (12) to reduce inter-FET source lead inductance. The FETs (22 & 24) are coupled to a set of conductors (16a, 16b, 16c & 16d) which are formed on the substrate (12). These conductors (16a, 16b, 16c & 16d) are deployed in a substantially symmetric pattern about the active devices (14d & 14e) as opposing pairs in registration across the substrate (12), and are located in positions that are substantially equidistant from the active devices (14d & 14e). The conductors (16a, 16b, 16c & 16d) are arranged to allow an equal and opposed input signal (i) to flow through conductors 16a and 16b. An amplified signal gi (gain x input current) is produced in conductors 16c and 16d. Electrically conductive vias (17) may extend between faces (12a) and (12b) to facilitate electrical connections between the sources of the active devices (14d & 14e) on either side of the substrate (12). Power is supplied to the active devices (14) through terminals (18). A miniature heat pipe (19) may be formed within substrate (12) and contains a liquid, gas or solid material that is capable of conducting unwanted heat away from the active devices (14d & 14e) or for temporarily storing unwanted heat from the active devices.