Process oriented logic simulation having stability checking

Abstract

A logic simulator for optimal configurability of combinatorial and sequential logic circuits in a simulated behavioral form. The present invention contains process oriented functional blocks with event posting to eliminate unnecessary evaluations in logic simulation. Also, the present invention manages a process to logic signal(s) and logic signal to process(s) sensitivity relationship(s) which reduces the traditional overhead of event scheduling and stabilization. The processing logic of the preferred embodiment is operably disposed within the random access memory and executed by the processor of a computer system. Upon activation of the present invention and initialization of all signals, a test is performed to determine if the logic network being simulated is in a stable condition. If the logic network is not stable, a loop is initiated for propagating signals and updating signal states throughout the logic network. Once the logic is propagated, the new state for all signals for which a state transition has occurred is set. Once the new states of signals have been set, a test is performed to determine if a new state has been encountered. A loop continues as long as signals transition to a new state. When a new state is not encountered, but the logic network has still not stabilized, a new state is forced and a new loop iteration is initiated. These loop iterations continue until the logic network stabilizes and simulation processing terminates.