Multiprocessor system using odd/even data buses with a timeshared

Abstract

Bus arrangements are disclosed for interconnecting processors and main memory modules of a shared memory multiprocessor system. A single address bus interconnects all processors and memory modules, but odd and even memory modules communicate data to and from the processors via an odd and an even data bus. Each reading of memory occupies four bus cycles on one of the data buses. On the address bus, two of each of the four cycles are available for addressing odd and even memory modules, and the other two are available for sending invalidation addresses to the caches of the processors. The single address bus is used for transmitting a relatively narrow (32-bit) address word throughout the system, one address on each bus cycle, while the data buses are time shared to transmit a wide data word (256-bit) in four bus cycles, and each data bus is only connected to half of the main memory modules. Such an arrangement makes efficient use of limited bus resources to transmit information when and where it is needed.