Memory stream buffer

Abstract

A memory system has a stream buffer with several performance-enhancing features. Two distinct sets of latches receive data from the memory array. One set feeds the stream buffer, while the other holds memory data that is destined for a system bus. The dual-latch configuration allows stream buffer fills to proceed even if system bus stalls prevent the memory data latch from being timely emptied. The memory controller prefetches a number of data blocks depending on the interleave factor of the memory system, as well as in response to control information from the CPU that can override the interleave-based number in some system configurations. The stream buffer employs a history buffer containing the addresses of recently-read memory locations in order to declare a new stream. The addresses of memory reads are normally entered into the history buffer on a round-robin basis. However, the addresses of those reads that hit in the stream buffer are not entered, thus improving the overall efficiency of the stream buffer. Also, the memory refresh controller treats stream buffer hits as memory refresh opportunities. Finally, a block of control/status registers within the memory controller is accessible in two distinct address ranges, so that the memory controller may easily be used in different hardware configurations.