Constant delay interconnect for coupling configurable logic blocks

Abstract

A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. The interconnect network has longlines and programmable interconnect points (PIP's). PIP's are symmetrical distributed in a partially populated fashion within the interconnect network such that a substantially same signal propagation delay develops for each signal routed along a program-selected longline from a CLB adjacent to that longline to an IOB adjacent to that longline.