The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 1996
Filed:
Nov. 06, 1992
Carlos A Gomez, Austin, TX (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
A system for interfacing wafer sort prober apparatus and packaged IC handler apparatus to a common test computer is provided that includes a single motherboard and at least one daughter board. The motherboard includes a probe card interface area having a plurality of contactors that mate with symmetrical connectors provided on a probe card. The probe card includes a series of contact probes adapted to make electrical connection to a semiconductor wafer. The motherboard also includes a hole in its center to allow visual inspection and alignment of the wafer when it is positioned beneath the motherboard. A test head interface area is also provided on the motherboard and includes a plurality of contactors that mate with symmetrical contactors provided on a test head assembly of the test computer. The motherboard further includes a daughter board interface area having a plurality of contactors that mate with symmetrical contactors provided on each daughter board. A connector is provided on each daughter board that mates with an IC contactor unit. As a result, a common interface board can be used during both wafer sort testing and packaged IC testing. Cost is thereby reduced since entirely separate boards are not required. The motherboard incorporates interconnecting lines and support interface circuitry common to both wafer sort and packaged IC testing. In addition, by using a packaged IC standard unit (that is, an IC that is known to be completely functional), debugging of the motherboard interconnecting lines and support circuity for the wafer sort configuration is simplified. Debugging of the wafer sort configuration is simplified since the daughter board can be attached directly to the motherboard independent of a prober apparatus, and thus mechanical access to the motherboard is not obstructed.