The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 1996

Filed:

Mar. 07, 1994
Applicant:
Inventors:

Anantakotiraju Vegesna, Austin, TX (US);

Jayachandra B Avula, Austin, TX (US);

Peter H Jewett, Austin, TX (US);

Yatin G Mundkur, Austin, TX (US);

Assignee:

Ross Technology, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
395800 ; 395375 ; 364D / ; 3642318 ; 364228 ; 364258 ; 3642954 ;
Abstract

An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.


Find Patent Forward Citations

Vegesna, Anantakotiraju. (1996). Central processing unit architecture with symmetric instruction (U.S. Patent No. 5488729). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5488729

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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