The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 1996

Filed:

Jun. 28, 1994
Applicant:
Inventors:

Eiji Yamada, Tenri, JP;

Hitoshi Takeuchi, Kitakatsuragi, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ;
U.S. Cl.
CPC ...
375340 ; 375371 ; 341122 ; 327 91 ;
Abstract

A digital data detector samples a signal at twice the data rate and calculates a phase interval from a zero crossing point to the current sampling point. The phase of the current sampling point is predicted based on the phase of a sampling point located before the current sampling point, the phase of a sampling point located at least two points before the current sampling point, and a zero crossing detection signal. A predicted error is calculated between a calculated phase interval and a predicted current phase. The frequency band of the predicted error is limited, and the phase of the current sampling point is calculated according to the band-limited predicted error, the predicted current phase, and the zero crossing detection signal. A data detection clock is detected in synchronization with a received digital data according to the calculated phase of each sampling point. A digital data value is detected using the phase interval, the calculated current phase, and sampling data. The predicted error is band-limited, and the phase of the current sampling point is calculated to follow only fluctuation due to wow and flutter in a relatively low frequency band. Since a clock signal is detected for data detection according to the calculated phase, digital data can be detected with a small data error rate even from received digital data having a low signal to noise ratio.


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