The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 1996

Filed:

Oct. 04, 1993
Applicant:
Inventor:

William F Heybruck, Charlotte, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 222 ; 371 221 ;
Abstract

Disclosed are methods and apparatus for a testing a field programmable logic gate array. In the method the non-volatile gates are set to a testable setting. The programmable logic array is then configured into (1) a pseudo random pattern generator, (2) a multiple input signature register, (3) a signature comparator, and (4) AND-plane and OR-plane logic array areas. A pseudo random set of test pattern vectors is applied to the programmable logic array from the pseudo random pattern generator. The output is captured in the multiple input signature register and compared in the comparator. Finally, individual non-volatile floating gate field effect transistors are selectively set to provide the desired set of sums of products.


Find Patent Forward Citations

Heybruck, William. (1996). Method and apparatus for field testing field programmable logic arrays (U.S. Patent No. 5488612). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5488612

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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