Semiconductor memory device

Abstract

A semiconductor memory device is disclosed, having a plurality of memory cells, from which cell data is read out, based on at least one control signal provided to the memory device. The memory device includes a transfer gate which receives read data from one of the memory cells, a latch circuit which latches the read data sent from the transfer gate, and an output buffer which outputs data produced in accordance with the latched read data. The memory device further includes a transfer gate controller, which produces a latch control signal based on the control signal and supplies the latch control signal to the transfer gate to control an ON/OFF action of the transfer gate. A delay circuit, incorporated in the gate controller, controls level-switching timing for the latch control signal such that after switching the level of the control signal, the transfer gate is turned off with a predetermined delay.