The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 1996
Filed:
Oct. 06, 1993
Hiroshi Sakamoto, Kumamoto-shi, Kumamoto, JP;
Hideki Tamura, Moriyama, JP;
Kaoru Furukawa, Hikone, JP;
Other;
Matsushita Electric Works, Osaka, JP;
Abstract
An inverter power supply operating at a high efficiency to provide an AC voltage to a load. The power source includes a DC voltage source and an output transformer with a primary winding, secondary winding, and a feedback winding. An FET is connected in series with the primary winding across the DC voltage source. The primary winding is connected to a capacitor to form a L-C resonant circuit which, in response to the switching of FET, provides across the primary winding an oscillation voltage to be applied through the secondary winding to drive a load, while inducing a feedback voltage across the feedback winding. The oscillation voltage is allowed to go negative at a point between FET and the primary winding. A biasing capacitor is connected to apply an offset voltage which is additive to the feedback voltage so as to give a bias voltage to FET. The power supply is characterized to include a level detector which issues a zero voltage signal when the oscillation voltage is detected to lower to at least zero level, and to include a pulse generator which, in response to the zero voltage signal, produces a pulse of a predetermined pulse-width which overrides the feedback voltage in such a manner as to enable FET to turn on for a ON-period determined by the pulse-width only after the oscillation voltage is lowered to at least zero level, whereby avoiding FET from flowing a current while the oscillation voltage is still positive and therefore reducing a switching loss.