The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 1996
Filed:
Oct. 04, 1994
Sridhar Vajapey, Sugarland, TX (US);
Paul W Krause, Sugarland, TX (US);
John M Bach, Stafford, TX (US);
Texas Instruments, Dallas, TX (US);
Abstract
A multifunction data storage register is provided having at least one first register cell having a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input exclusive not OR circuit having a first input connected to said first output signal of said first input multiplexer and a second input connected to a cell output signal and having a third output signal, a first shift register latch having an input connected to said third output signal of said first input exclusive not OR circuit and having a fourth output signal, a first output exclusive not OR circuit having a first input connected to said fourth output signal of said first shift register latch and a second input connected to a feedback signal and having a fifth output signal, and a first output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a first cell output signal, and at least one second register cell having a second input multiplexer for selecting between two input signals responsive to said one or more control signals and having a seventh output signal, a second input exclusive not OR circuit having a first input connected to said seventh output signal of said second input multiplexer and a second input connected to a cell output signal and having an eighth output signal, and a second shift register latch having an input connected to said eighth output signal of said second input exclusive not OR circuit and having a second cell output signal.