The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 1996

Filed:

May. 26, 1994
Applicant:
Inventors:

B Jayant Baliga, Raleigh, NC (US);

Jacek Korec, Morfelden-Walldorf, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257132 ; 257133 ; 257137 ; 257138 ; 257331 ; 257332 ; 257334 ; 257378 ;
Abstract

A gate-controlled bipolar transistor with buried collector includes a wide base bipolar transistor in a semiconductor substrate having a trench at a face thereof. A dual-channel insulated-gate field effect transistor (IGFET) is also included adjacent a sidewall of the trench for providing gated turn-on and turn-off control of the bipolar transistor. The bipolar transistor includes a buried collector region at a bottom of the trench, which is electrically connected to a cathode contact at the face. An emitter of the transistor is electrically connected to an anode contact at an opposing face of the substrate. For turn-on, the base of the bipolar transistor is electrically connected to the cathode contact upon the application of a gate bias signal to the IGFET. By electrically connecting the base to the cathode contact, forward conduction can be established once the anode contact is appropriately biased relative to the cathode contact. Latch-up can also be prevented by using the buried collector region as a diverter region to prevent the regenerative conduction between P--N--P--N coupled regions of the transistor.


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