Autoranging digital analog phase locked loop

Abstract

An autoranging digital/analog (D/A) phase locked loop (PLL) 10 includes a frequency discriminator circuit 12 connected to a shift register 14. Shift register 14 is connected to a voltage controlled oscillator circuit (VCO) 16. VCO 16 is connected to generic counter 17. Counter 17 is optional in this preferred embodiment. Counter 17 is connected to a phase detector 13 and frequency discriminator 12. Phase detector 13 is connected to a charge pump control circuit 15. Charge pump control circuit 15 is also connected to VCO 16. A second generic counter 11 is connected to frequency discriminator 12. Second counter 11 is also optional in this preferred embodiment. First generic counter 17 and second generic counter 11 can be implemented to reduce the phase detector frequency relative to VCO 16 or a reference clock signal frequency. Ratios of M to N allow frequency multiplication or division of VCO 16 relative to the reference clock signal frequency. A method for achieving phase lock between a first signal and a second signal, in accordance with the present invention, comprises the steps of comparing the phases of the first signal and the second signal, adjusting the frequency of the second signal in a digital fashion until the phases of the first signal and second signal are within a predetermined phase relationship; and adjusting the frequency of the second signal in an analog fashion until a phase lock is obtained between the first signal and the second signal.