The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 1996

Filed:

Nov. 02, 1994
Applicant:
Inventors:

Takakuni Douseki, Kanagawa, JP;

Junzo Yamada, Kanagawa, JP;

Yasuyuki Matsuya, Kanagawa, JP;

Shinichirou Mutou, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 33 ; 326 81 ; 327541 ;
Abstract

A logic circuit includes a low-threshold logic circuit, a pair of first and second power lines, a first dummy power line, and a first high-frequency logic circuit. The low-threshold logic circuit has a logic circuit element constituted by a plurality of low-threshold field effect transistors. The pair of first and second power lines supply power to the low-threshold logic circuit. The first dummy power line is connected to one of power source terminals of the low-threshold logic circuit. The first high-threshold control transistor is arranged between the first dummy power line and the first power line.


Find Patent Forward Citations

Douseki, Takakuni. (1996). Cmos logic circuits having low and high-threshold voltage transistors (U.S. Patent No. 5486774). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5486774

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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