The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 1996
Filed:
Jun. 28, 1991
Daniel R Brasen, San Francisco, CA (US);
Sunil V Ashtaputre, San Jose, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A floor-plan of component blocks of logical circuits, including the symbolic routing of major connection networks, is produced as part of the process for laying out an integrated circuit on a chip. The floor-plan is produced before performing optimized placement and routing of logical circuits within component blocks of the VLSI circuit. First, the logical circuits are apportioned into component blocks. Then, an initial lay out of the component blocks of the VLSI circuit is performed. The major connection networks are routed between the component blocks so that the major connection networks are connected to connection areas within the component blocks. The initial lay out of component blocks is adjusted as necessary in order to take into account the addition of the major connection networks. Once any needed adjustments are made, routing guidance information is generated as part of the floor plan. The routing guidance information indicates locations and sizes of the major connection networks.