Phase-locked oscillator arrangement

Abstract

A phase-locked variable frequency oscillator arrangement includes a voltage controlled oscillator (VCO) which is controlled by a control signal produced by charging or discharging of a capacitor in a charge pump circuit, the charge pump circuit including current sources driven by up or down command signals from a phase detector which detects the phase of the VCO output. When the command signals are simultaneously active, a logic gate circuit supplies a reset pulse to the phase detector via a delay device which is adapted to the rise times of the current in the current sources. The delay device includes a transistor (the 'annexed' transistor) which forms a switched pair with one of the transistors which form the current sources. The reset signal is produced when the current of the annexed transistor reaches a selected fraction of its normal current, after being turned on by the logic gate circuit. Such circuit arrangement avoids a so-called 'dead zone' of uncorrectable small phase errors around a nominal zero phase shift condition.