The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 1996

Filed:

Feb. 26, 1993
Applicant:
Inventors:

Mark S Isfeld, San Jose, CA (US);

Bruce W Mitchell, San Jose, CA (US);

Assignee:

3Com Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39520003 ; 395857 ; 395500 ; 3642285 ; 3642383 ; 36493147 ; 364D / ;
Abstract

An internetwork device which manages the flow of packets of I/O data among a plurality of network interface devices includes a bus coupled to the plurality of network interface devices, a core memory storing only packets of I/O data and control structures needed by the plurality of network interface devices, and a processor including local memory isolated from the core memory storing routines and internetwork information involved in updating control structures and control fields in the packets of I/O data to direct movements of packets of I/O data among the plurality of network interface devices. A bus-memory interface is provided through which transfers of packets of I/O/data and control structures used by the plurality of network interface devices are conducted between the core memory and the bus. A processor-memory interface is provided through which transfers of data to or from control structures or control fields in packets of I/O data are conducted between the core memory and the processor. Finally, a processor-bus interface is included through which configuration information concerning control structures and I/O data buffers in the core memory are transferred between the plurality of network interface devices and the processor across the bus. The processor-bus and processor-memory interfaces include structures for decoupling processor accesses to configuration stores in the plurality network interface devices and to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.


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