Device for detecting transmission errors in balanced two-wire bus lines

Abstract

A device for monitoring balanced two-wire bus lines and two-wire but interfaces has first, second and third comparison circuits for comparing the wire potentials with one another and with a fixed reference voltage, and two shift registers or counters as well as at least one pulse generator for deriving reset pulses from each change in sign of the potential comparison of the two bus conductors with one another. The shift registers or counters are respectively reset by the reset pulses. Result signals produced from the comparison of the bus potentials with a fixed reference voltage can be fed to the shift registers or counters for the purpose of shifting or incrementing said registers or counters respectively. The register length or number of counter stages can be selected as a function of a desired bit error tolerance depth. The device can be extended by a self-resetting system after temporary bus disturbances. The device is also programmable, and thereby universal, and because of an integration capability using standard technology and having a very low space requirement is suitable as a compilable standard cell for possible bus chip designs. The device is operable in cooperation with software routines of a decentral bus test system as a test receiver for analyzing bus disturbances.