The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 1996
Filed:
Jan. 26, 1994
Motorola Inc., Schaumburg, IL (US);
Abstract
A mantissa addition system (2) having a mantissa adder (6) for adding two mantissas provides an addition result a plurality of bits arranged in sub-groups. The mantissa addition system also has a flag generator which generates a flag for each sub-group: each flag having an active state when all the bits in the respective sub-group are zero and an inactive state when at least one of the bits in the respective sub-group is non-zero. A first detector (46) determines the most significant flag that has the inactive state and provides a first control signal representative of the detected most significant flag. A first shifter (40) shifts the groups of bits of the addition result in response to the first control signal so that the sub-group of bits corresponding to the detected most significant flag is the most significant group. A second detector (48) detects the most significant bit of the most significant sub-group of the shifted result that is non-zero and provides a second control signal representative of the detected most significant bit. A second shifter (42) shifts the plurality of bits of the shifted result in response to the second control signal so that the detected most significant non-zero bit is the most significant bit. The output (8) of the second shifter represents the normalised addition result. The shift information (N) is generated by logic means (52, 54) from the first and second control signals.