Power-on reset circuit

Abstract

A power-on reset circuit is disclosed comprising a capacitor for being charged to a desired voltage and then being discharged; a Schmitt trigger circuit for discriminating the voltage discharged from the capacitor and transitioning instantaneously its output when the discharged voltage reaches a predetermined level to output a reset signal, and then transitioning its output again after the lapse of a predetermined time period to maintain a constant voltage; a state latch circuit for inputting the output of the Schmitt trigger circuit, the state latch circuit being transitioned after the lapse of a predetermined time period from generation of the reset signal by the Schmitt trigger circuit and then remaining at the transitioned state; and an inverter for inverting an output voltage of the state latch circuit and applying the inverted output voltage to the capacitor. In accordance with the invention, the power-on reset circuit generates a reset pulse regardless of a voltage rise time, consumes little or no appreciable power after generation of the reset pulse, occupies a small space due to its efficient construction, and has a readily adjustable reset time.