The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 1996

Filed:

Dec. 23, 1993
Applicant:
Inventor:

Takashi Tatsumi, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395800 ; 395375 ; 364761 ; 364748 ; 3649373 ; 3642583 ; 3642595 ; 364D / ;
Abstract

A divider comprising a first and second normalizing circuits (5, 6) each which holds a hexadecimal-normalized mantissa data of a dividend and divisor respectively, a selector (7) which inputs the mantissa outputted from the first normalizing circuit (5), a remainder data outputted from a latch (13), a borrow signal (16) of a subtracter (8) which subtracts the mantissa data of the divisor from the mantissa of the dividend data of the remainder data, and control signals 21, 22, 23 respectively indicating a first, second and third and after third division cycles, through-outputs the mantissa data of the dividend in the first division cycle, shifts the mantissa data outputted from the first normalizing circuit (5) to the right by three bits and outputs it when the borrow signal (16) indicates '0' in the second division cycle, shifts the mantissa data outputted from the first normalizing circuit (5) to the left by one bit when the borrow signal (16) indicates '1', and through-outputs the remainder data outputted from the latch (13) in the third division cycle, and a dividing circuit. (100) which calculates a quotient data and a remainder data by using data outputted from the selector (7) and the mantissa data outputted from the second normalizing circuit (6).


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