The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 1996

Filed:

Apr. 11, 1995
Applicant:
Inventors:

Philip A Murphy, Jr, King of Prussia, PA (US);

Wayne A Genetti, Phoenixville, PA (US);

Gunnar K Gunnarsson, West Chester, PA (US);

Edward J Pullin, Norwood, PA (US);

Steven A Thompson, Coatesville, PA (US);

Robert H Tickner, Jeffersonville, PA (US);

Gary C-F Wu, Audubon, PA (US);

Assignee:

Unisys Corporation, Blue Bell, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
395650 ; 395821 ; 395427 ; 395800 ; 364230 ; 3642303 ; 3642833 ; 3642834 ; 3642456 ; 364D / ; 3649644 ; 3649671 ; 364D / ;
Abstract

A computer system performs memory to memory transfer, task scheduling and I/O request handling via a group of dedicated processors (e.g. a memory interface unit, an I/O unit, a data transfer unit, and a task control unit). The memory interface unit facilitates data interaction between the memory and the remainder of the system. The I/O unit is coupled to the memory interface unit and performs high level I/O job functions including I/O job scheduling, I/O job path selection, gathering of job statistics and device management. The data transfer unit is coupled to the memory interface unit and moves data between memory locations. The task control unit, coupled to the memory interface unit, allocates and deallocates events, maintains the status of tasks running on the system and schedules the execution of tasks. A hierarchical error reporting scheme is used by all of the processors.


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