The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 1996
Filed:
Jul. 28, 1993
Toyohito Hatashita, Kanagawa, JP;
Motoharu Taura, Kanagawa, JP;
Toshihiko Shimizu, Kanagawa, JP;
Hiroshi Umeoka, Kanagawa, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A multi-memory apparatus, configured only with identical memory units with access to the common system bus, provides secure data identity in the event of various errors by using synchronous as well as parallel operation. A memory unit in a multi-memory apparatus includes a refresh request circuit, a bus control circuit, a bus-response circuit as well as a control circuit. A master refresh request circuit issues a memory-refresh request by using the bus clock and a backup refresh request circuit issues a memory-refresh request by a trigger from the master memory. A master bus control circuit responds to the system bus and a backup bus control circuit prohibits the unit from responding. A master bus-response control circuit allows the bus control circuit to respond to the system bus and changes mode between memory units from master/backup to backup/master in the event of an error detected in the master memory unit.