The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 1996
Filed:
Dec. 06, 1993
Kazuo Itoh, Sayama, JP;
Kazuhiko Narita, Sayama, JP;
Shuichi Kitazawa, Sayama, JP;
Masanori Tokoi, Sayama, JP;
Ayumi Nakajima, Sayama, JP;
Hiroshi Sekine, Sayama, JP;
Abstract
A method of and an apparatus for producing solid models, in which input data consisting of the coordinates of terminal points and a formula of a curved line of each arc of a given wire frame model is read. The coordinates of a node and a set of arcs connected thereto are determined based on the input coordinates of the terminal points. A set of arcs looping around an indivisible surface of the wire frame model are specified as the outermost line surrounding the whole wire frame model. A region of the wire frame model surrounded by the outermost line or division lines is divided into two new partial wire frame models by a new division line starting from a node located on the outermost line or the division lines, traversing the region without making a loop, passing along each of the arcs included in the region only once, and reaching another node located on the outermost line or the division lines. The division is repeated until there remains no arc which has not yet been passed through in any of the partial wire frame models. A a set of arcs looping around each of the further-indivisible partial wire frame models is defined as surface loop.