The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 1995
Filed:
Oct. 12, 1993
Stephen W Olson, Wilmington, MA (US);
James B MacDonald, Dracut, MA (US);
Richard W Lones, Amherst, NH (US);
Wang Laboratories, Inc., Lowell, MA (US);
Abstract
A method, and circuitry that operates in accordance with the method, for generating an entry for a translation buffer in a data processor that employs virtual memory addressing. The method includes the first steps of storing a Faulted Virtual Address in a first register (96) and a Zone Table Address (ZTA) in a second register (94). In response to the execution of a micro-instruction, a next step forms an address in memory of a Zone Table Entry (ZTE) by selectively combining a first portion of the content of the first register with the content of the second register, while simultaneously testing the ZTA for physical address mapping. In response to an execution of a next micro-instruction, a next step accesses the ZTE with the formed address, and forms an address in memory of a Segment Table Entry (STE) by selectively combining a second portion the content of the first register with a content of the ZTE, while simultaneously testing the ZTE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the STE with the formed address, and forms an address in memory of a Page Table Entry (PTE) by selectively combining a third portion of the content of the first register with a content of the STE, while simultaneously testing the STE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the PTE with the formed address and selectively combines the content of the STE with the content of the PTE and outputs the combination as the translation buffer entry, while simultaneously testing the PTE for a Page fault.