The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 1995
Filed:
Feb. 14, 1995
Masahiro Ueda, Amagasaki, JP;
Yasushi Hayakawa, Itami, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
There is disclosed a signal processing device which includes a pre-processing circuit (31) for performing a serial-to-parallel conversion on an intermediate signal (M.sub.2) at a PECL level, the serial-to-parallel conversion at the PECL level being permitted to deal with a high frequency, and a level converter circuit (12) for performing a conversion from the ECL to PECL levels both having the same logic level width, which conversion consumes less power than a conversion between the ECL and CMOS levels having different logic level widths. The level conversion of a parallel signal requires less power consumed than a level conversion of a serial signal. The signal processing device further includes a level converter circuit (13) for performing a conversion into the CMOS level after obtaining an intermediate signal (M.sub.3) which is a parallel signal. An intermediate signal (M.sub.4) is at the CMOS level and has a low frequency. The signal processing device which operates at the CMOS level processes the high-frequency signal at the ECL level for reduction in consumed power.