The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 1995
Filed:
Jun. 01, 1992
Applicant:
Inventor:
James M Rugg, Mesa, AZ (US);
Assignee:
Motorola, Inc., Schaumburg, IL (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01F / ;
U.S. Cl.
CPC ...
364490 ; 364491 ;
Abstract
A BiCMOS integrated circuit design having an oversized isolation area surrounding circuit elements which are non-scaleable is provided. The non-scaleable circuit elements can be removed from the layout, and the remaining scaleable elements shrunk by a CAD system. After shrinking the scaleable elements and the isolation area, the non-scaleable elements are returned to the layout at their original size, and located within the scaled-down isolation area.
Quick Actions:
Rugg, James. (1995). Shrinkable bicmos circuit layout (U.S. Patent No. 5477467). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5477467
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile