The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 1995

Filed:

Mar. 16, 1994
Applicant:
Inventor:

Yasuhiko Maki, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H / ;
U.S. Cl.
CPC ...
327161 ; 327262 ; 327270 ;
Abstract

A data-hold timing adjustment circuit having resistance wires to which a power-supply voltage is supplied, formed along numerous flip-flops. MOS variable capacitors 3i and 4i (i=1 to n) are connected at one electrode to the data input end of the flip-flops and at another electrode to the resistance wires. The composite capacitance of the MOS capacitors becomes larger as the value of i increases, independent of the voltage level of the data input end of the flip-flops. When the potential of the data input end of the flip-flop shifts from a high/low level to a low/high level, this shift is delayed more as the value of i becomes larger, while the clock input to the flip-flop is delayed more as the value of i becomes larger.


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