Pipelined computer with half machine cycle alternating write control for

Abstract

In a data processing system, arithmetic/logic units, each with a different number stages, are pipelined for executing arithmetic/logic instructions stored in main memory in full machine cycles. One of the outputs of the arithmetic/logic units is selected. In response to a memory access instruction, data is fetched from the main memory and stored into general registers in which the results of instruction execution from the arithmetic/logic units are also stored. A selector has a first input terminal which receives the selected output of the arithmetic/logic units, a second input terminal for receiving the fetched data, and an output terminal coupled to the general registers. In response to half machine clock pulses, the selector alternately establishes a first path between the first input terminal and the output terminal and a second path between the second input terminal and the output terminal during mutually exclusive times of half machine cycle.