Flash write circuit for a semiconductor memory device

Abstract

A semiconductor memory device having a plurality of memory blocks and a plurality of I/O control circuits operatively associated with respective ones of the memory blocks. Each of the I/O control circuits includes a flash write enable signal generator responsive to a flash write mode indication signal and a respective memory block address signal, for generating a memory block specific flash write enable signal. Each of the I/O control circuits further includes a plurality of first column selectors connected between respective first alternate pairs of bit lines and respective first data input/output lines, a plurality of second column selectors connected between respective second alternate pairs of bit lines and respective second data input/output lines, and a plurality of flash write control logic circuits responsive to the memory block specific flash write enable signal and a respective one of a plurality of column select signals for generating a corresponding plurality of column selector drive signals. The first column selectors are responsive to respective ones of the column selector drive signals for selectively coupling data to/from respective ones of the first alternate pairs of the bit lines from/to the first data input/output lines. The second column selectors are responsive to respective ones of the column selector drive signals for selectively coupling data to/from respective ones of the second alternate pairs of the bit lines from/to the second data input/output lines.