Double scan circuit for inserting a new scan line between adjacent scan

Abstract

A double scan circuit has first and second data converters for converting n-bit real line data and n-bit interpolated line data into 2n-bit data; first and second RAMs in which the real line data and the interpolated line data are stored, respectively; a memory controller for generating a write/read control signal for the first and the second RAMs, a write address and a read address whose speed is double that for the write address, for outputting them to the first and second RAMs, and for generating a mixing control signal for mixing the original line data and the interpolated line data stored in the first and second RAMs for double scanning; and a multiplexer for selecting one between the 2n-bit real line data and the 2n-bit interpolated line data generated from the first and second RAMs in accordance with the mixing control signal and the real/interpolated line control signal and for producing the selected one as n-bit double scan data. This circuit facilitates VLSI implementation compared with a conventional double scan circuit using FIFO-type memories.