The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 1995

Filed:

Feb. 23, 1994
Applicant:
Inventor:

Takayuki Kimura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395550 ; 364270 ; 3642702 ; 3642715 ; 3642591 ; 364D / ; 395800 ;
Abstract

A selector 11 selects one of a plurality of reference clock signals based upon a selection signal. A hardware reset signal 103 is delayed by a predetermined time. The selection signal is sent to the selector responsive to a set signal. The sending of the selection signal is stopped responsive to the delayed hardware reset signal. The set signal is delayed by a predetermined time. A first flip-flop 13 is set in response to the hardware reset signal or a software reset signal, is supplied with the delayed set signal as a count input, and is supplied with low level as a data input. A second flip-flop 16 receives a logic AND signal of an output signal from the selector 11 and the hardware reset signal as a count input and receives a logic OR signal of the output of the first flip-flop 13 and an inverted output of the second flip-flop 16 as a count signal, and generates a clock output.


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