The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 1995
Filed:
Dec. 28, 1994
Miroslaw Guzinski, Lawrenceville, NJ (US);
Ilyoung Kim, Plainsboro, NJ (US);
AT&T Corp., Murray Hill, NJ (US);
Abstract
An N stage counter includes peripheral circuitry for testing the operability of the counter. The peripheral circuitry includes gating means coupled between certain stages of the counter for partitioning the counter into at least first and second counter sections during a testing mode. During the testing mode, the N counter stages are reset to an all zero condition and this resettability capability is detected. During the testing mode, the N counter stages are also set to a predetermined value and the settability of the counter stage to a non-zero condition is also detected. During one phase of the testing mode, the first section counts a predetermined number of clock cycles while all counts produced at the outputs of all the stages of the second section are totalled in a register means. During another phase of the testing mode, the second section counts a predetermined number of clock cycles while all the counts produced at the outputs of all the stages in the first section are totalled in the register means. Thus, during the one phase, the first section functions as a timer for the second section and during the second phase, the second section functions as a timer for the first section. The counts generated by the first and second sections are subsequently totalled and compared with a predetermined number to ascertain the operability of the counter.