Digital signal processor delay equalization for use in a paging system

Abstract

A method and apparatus provide an equalization time delay to synchronize a plurality of paging transmitters in a simulcast paging system. A delay equalization circuit (41 ) appropriate for use with an analog input signal includes a coder/decoder (CODEC) (50) and a digital signal processor (DSP) (58). An analog input signal is digitized or sampled by an analog-to-digital converter (ADC) in the CODEC, producing corresponding digital values that are input to the DSP. The DSP employs a selected finite impulse filter to interpolate between the sampled digital values from the CODEC to provide enhanced resolution in delaying a signal output that is output. The DSP determines a major sample index and an interpolated filter index to achieve the desired equalization time delay. These variables define two delay intervals that are combined to provide the required equalization time delay. As each sampled digital value is produced, the delayed value is output and converted by a digital-to-analog converter (DAC) 54 in the CODEC to an analog signal having the corresponding required delay. By thus providing the appropriate equalization time delay to the signal transmitted by each paging transmitter in a simulcast paging system 20, differences in the time required for the analog signal to propagate from a paging terminal to each paging transmitter are compensated, thereby substantially eliminating phase interference in overlap zones of the paging transmitters.