The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 1995
Filed:
Jan. 31, 1995
Thomas D Gurley, Indianapolis, IN (US);
Gene K Sendelweck, Indianapolis, IN (US);
Thomas D Yost, Indianapolis, IN (US);
Thomson Consumer Electronics, Inc., Indianapolis, IN (US);
Abstract
A bias source (R7,R8,C24) connected to a summing amplifier (Q1) produces a first DC bias at the amplifier input (emitter) and a second DC bias at the amplifier output (collector). A first circuit node (B) is AC coupled (22) to a luminance signal source (Y1, 18), DC coupled via a first resistor (R4) to the input of the summing amplifier and DC coupled via a first amplifier (28) to a luminance load (Y3,30). A second circuit node (A) is AC coupled (20) to a chrominance signal source (C1,18), DC coupled via a second resistor (R3) to the input (emitter, Q1) of the summing amplifier and DC coupled via a second amplifier (26) to a chrominance signal load (C3,30). A third amplifier (Q2) provides DC coupling of the output of the summing amplifier (Q1) to a composite video signal load (E,40). Advantageously, the circuit provides component to composite conversion with plural buffered outputs which may exhibit different power gains, which are stable notwithstanding load impedance variations and which are DC biased by bias produced at the summing amplifier input as well as its output thereby simplifying the conversion and buffering.