The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 1995

Filed:

Aug. 03, 1994
Applicant:
Inventor:

Heinz Werker, Taufkirchen, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L / ; H03K / ; G06F / ;
U.S. Cl.
CPC ...
375376 ; 375374 ; 326 95 ; 327158 ; 327160 ; 327161 ;
Abstract

A phase-locked loop configuration includes a controllable delay device having a signal path with at least one inverter having supply lines, at least one field effect transistor having a load path, and at least one capacitor connecting the load path transversely to the signal path. A phase detector receives a reference signal and receives an input signal through the delay device. A first controller is connected downstream of the phase detector for controlling the load path of the at least one field effect transistor in the delay device. At least one pair of further field-effect transistors has load paths connected into the supply lines of the at least one inverter. A second controller is connected downstream of the phase detector for controlling the load paths of the further field effect transistors.


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