Method and apparatus for testing digital signals

Abstract

A logical circuit is tested by comparing at least one arbitrary bit of a logical signal among logical signals outputted from the logical circuit with an expected value corresponding to the correct level of the logical signal, and comparing a bit position at which the level of the logical signal changes with an expected change point indicating a bit position at which the level of the correct logical signal changes. Such a test can be performed using a tester having a first comparator for comparing a logical signal outputted from a logical circuit to be tested with an expected value corresponding to the correct level of the logical signal, during at least one arbitrary unit test cycle, a change point detecting unit for detecting a time of level change of the logical signal and outputting change point information, by comparing the logical signal delayed by the unit test cycle with the logical signal not delayed, an expected change point generator for generating an expected change point signal indicating a bit position at which the level of the correct logical signal changes, and a second comparator for comparing the change point information with the expected change point signal, wherein the logical circuit is tested using the comparison results of the first and second comparators.