The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 1995

Filed:

Mar. 05, 1993
Applicant:
Inventors:

Fu-Sheng Tsai, Northboro, MA (US);

William W Ng, Leominster, MA (US);

Assignee:

Digital Equipment Corporation, Maynard, MA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M / ;
U.S. Cl.
CPC ...
363 20 ; 363 21 ;
Abstract

Transformers (T1, T2), switches (M1) and (M2), rectifiers (DR1, DR2, DR3, DR4) and low-pass filter (LF, CF) form a basic power train circuit (12). Auxiliary switches (A1, A2), diodes (DS1, DS2) and capacitors (CS1, CS2) form active clamp circuit (10). The capacitances for (CS1, CS2) are chosen large enough such that the voltages (vCS1, vCS2) across the capacitors are essentially constant during several switching cycles. Switches (M1) and (A1) are driven by the signal (V.sub.G1), while switches (M2) and (A2) are driven by (V.sub.G2). When (M1) is turned OFF, the energies stored in the magnetizing and leakage inductances in (T1) will resonate with the output capacitance of (M1) first. When the voltage (V.sub.M1) across (M1) exceeds the voltage (V.sub.CS1) across (CS1), (DS1) conducts and (V.sub.M1) is clamped at (V.sub. CS1), which has a steady-state value of slightly less than two times the input voltage (E). During this interval, the capacitor (CS1) is charged by the leakage inductor current (i.sub.LK1). When (i.sub.LK1) reduces to zero, (DS1) stops conducting, and (V.sub.M1) decreases to the level of (E). When (M2) is triggered, (A1) is also triggered. Diodes (DS1) and (DS2) are both reverse-biased. The energy in capacitor (CS1) is discharged through (A2) back to (E). Meanwhile, transformer (T1) is being reset. When (M2) is turned OFF, (A2) is also turned OFF. Voltage (V.sub.M1) decreases to (E), and a similar process occurs for the following half switching cycle, with the roles of (M1, A1, DS1, CS1, T1) and (M2, A2, DS2, CS2, T2) interchanged, respectively.


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