The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 1995

Filed:

May. 24, 1993
Applicant:
Inventor:

Albert H Taddiken, McKinney, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
341 83 ; 341133 ; 3647462 ; 326134 ; 326135 ;
Abstract

Multiple resonant tunneling devices offer significant advantages for realizing circuits which efficiently convert values represented by multivalued number systems to conventional binary representation. In one form of the invention, a number represented by a range-4 base-2 word is converted into a conventional binary word (range-2 base-2) having the same value. The conversion is accomplished by a series of decomposition stages 53, each decomposition stage 53 producing an interim range-4 base-2 word and a binary digit, which becomes one of the digits of the binary output word. Preferably, the decomposition at each stage is accomplished by a set of range-4 base-2 to binary converters 50, each of which operates on a single digit of the interim word. Preferably, summation circuits 52 sum outputs of adjoining range-4 base-2 converters 50 to form the new interim word. The least significant digit of the output of the decomposition stage becomes a digit of the output binary word. Preferably, the range-4 base-2 to binary converters 50 are multi-level folding circuits 54 connected by a voltage divider. Preferably, the multi-level folding circuits contain multiple-peak resonant tunneling transistors 56 (e.g. an FET 58 and a multiple-peak resonant tunneling diode 60) which exhibit multiple negative differential transconductance. The novel circuits presented allow the results of multivalued logic operations to be translated to binary representation at very high speed. Additionally, because they make use of resonant tunneling devices, the novel converter circuits described herein may be fabricated with very few components.


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