Multiprocessor computer system having bus control circuitry for

Abstract

A multiprocessor system includes first and second microcomputers, a address decoding mechanism, and a ready signalling device. The address decoder is coupled to an address bus, to decode address information transferred by the second microcomputer, and supplies a request signal to a request signal input terminal of the first microcomputer. A bus control unit of the first microcomputer responds to the request signal to detect whether an internal bus of the first microcomputer is free from being used by the CPU, and outputs an acknowledge signal to an acknowledge signal output terminal when the internal bus is free. The ready signaling device is coupled to the acknowledge signal output terminal to supply the ready signal to a ready signal input terminal of the second microcomputer in response to the acknowledge signal outputted at the acknowledge signal output terminal and the request signal. The bus control unit of the first microcomputer further responds to a strobe signal transferred to a strobe signal input terminal through a strobe signal line from the second microcomputer to access an address of the internal memory by using the address information transferred to a set of first address terminals through the address bus and performs a data read/write operation on the address of the internal memory through the internal bus.