Read only type semiconductor memory device including address coincidence

Abstract

A read only semiconductor memory device includes a plurality of address coincidence detecting circuits, each of which has a specific address region assigned thereto and generates an address coincidence detecting signal when an input address signal designates an address in the assigned region. A priority circuit determines a priority order among the plurality of address coincidence detection signals from the plurality of coincidence detecting circuits. In accordance with a signal to which priority is given by the priority circuit, a data output terminal receives memory cell data read from a memory array or is fixed at a predetermined logical level. With respect to a memory address region containing a succession of only data of logic '1' or '0' (that is, a region with all '1's' or '0's'), data of a logical level predetermined by a switching circuit is output to the data output terminal. For this memory address region, fixed data, which is not read from the memory array, is outputted. Therefore, a defective bit in this memory address region can be repaired efficiently, resulting in a high product yield of the read only semiconductor memory device.