Circuit for increasing data-valid time which incorporates a parallel

Abstract

This invention relates generally to the accessing of random access access memory arrays and, more specifically to circuits and techniques for increasing the data valid time of such memory arrays without increasing either the access or cycle times of the array. This is accomplished by providing, during a read cycle, a read signal directly to an output driver and simultaneously providing, via a parallel path, a latch output to the same driver. The latch output is provided under control of the read signal and a returning portion of a clock pulse such that the latch output overlaps the direct read signal from a read/write amplifier. An output is provided from the latch until it is reset and may last well into the next read cycle even when a new read signal is present. The technique utilized, in addition to providing a longer data valid time, eliminates a response of the latch to spurious read signals because a latch output is not provided until the clock is deactivated and such spurious read signals are not present during the returning portion of the clock cycle. The approach utilized also has the advantage that delays associated with prior art serially disposed latches are eliminated.